The present invention relates to a method of forming an improved Bi-CMOS semiconductor device.
The Bi-CMOS semiconductor device has an integration of a complementary MOS device having a pair of n-channel and p-channel MOS field effect transistors and a bipolar transistor. The bipolar transistor exhibits high speed performances, whilst the CMOS device shows a switching operation with a small current or a small power and has a small occupied area.
The Bi-CMOS semiconductor devices may be integrated as a circuitry which includes transistor-transistor logic (TTL) circuit and emitter-coupled logic (ECL) circuitry. Some of the transistor-transistor logic (TTL) circuit comprise only bipolar transistors, whilst another of the transistor--transistor logic (TTL) circuits comprises an integration of the CMOS device and the bipolar transistor. Namely, a Bi-CMOS TTL circuit has the integration of the CMOS device and the bipolar transistor. The emitter-coupled logic (ECL) circuit has the bipolar transistors.
Usually, both the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit may be integrated and both circuits are applied with power voltages different from each other. For example, the transistor-transistor logic (TTL) circuit is connected to a high voltage line applied with a voltage of 3.3V and a ground line having the ground potential, whilst the emitter-coupled logic (ECL) circuit is connected to a high voltage line applied with a voltage of 3.3V and a low voltage line applied with a voltage of -2V In this case, the high voltage line applied with a voltage of 3.3V is commonly used for both the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit. The ground line having the ground potential is connected to the transistor-transistor logic (TTL) circuit. The low voltage line applied with a voltage of -2V is connected to the emitter-coupled logic (ECL) circuit.
When the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit are integrated on a semiconductor chip, the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit receive power voltages different from each other, for which reason it is required to electrically isolate the transistor-transistor logic (TTL) circuit from the emitter-coupled logic (ECL) circuit. Since the transistor-transistor logic (TTL) circuit has both the CMOS device and the bipolar transistor, it is also required to electrically isolate the CMOS device from the bipolar transistor.
If the electrical isolation between the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit is incomplete, then noises generated in any one of the transistor-transistor logic (TTL) circuit and the emitter-coupled logic (ECL) circuit may provide an influence to the opposite one in operation. Also if the electrical isolation between the CMOS device and the bipolar transistor is incomplete, then noises generated in any one of the CMOS device and the bipolar transistor may provide an influence to the opposite one in operation.
In any event, the CMOS device and the bipolar transistor are integrated in a single epitaxial layer of p-type or n-type which is formed over a semiconductor substrate, wherein the CMOS device and the bipolar transistor are positioned adjacent to each other but electrically isolated from each other.
Since the complete electrical isolation between the CMOS device and the bipolar transistor is required, a p-well region and an n-well region are provided at a boundary between the CMOS device region and the bipolar transistor region wherein one of the p-well region and the n-well region is formed in the form of island in the other one of the p-well region and the n-well region. Namely, the p-well region and the n-well region form double surrounding structure whereby the occupied area of the Bi-CMOS device is enlarged. This means that the density of the integration of low.
In the Japanese laid-open patent publication No. 3-80565, it is disclosed that the n-channel MOS field effect transistor and the n-p-n bipolar transistor are isolated by the p-well in a plane view. Laminations of a low impurity concentration n-type buried layer and a high impurity concentration n-type buried layer are provided under the n-channel MOS field effect transistor and the n-p-n bipolar transistors so that the n-p-n bipolar transistor has a parasitic capacitance reduced by the buried layer. The reduction in parasitic capacitor of the n-p-n bipolar transistor shortens a delay time of signal transmission.
Since, however, the p-well is provided between the n-channel MOS transistor region and the n-p-n bipolar transistor region to isolate the n-channel MOS transistor region from the n-p-n bipolar transistor region.
This structure makes it difficult to reduce the occupied area of the Bi-CMOS semiconductor device.
In the Japanese laid-open patent publication No. 62-174965, there is disclosed an invertor circuit having the Bi-CMOS semiconductor device. An n+-type buried layer is formed over a p-type semiconductor substrate. An n-type epitaxial layer is formed on the n+-type buried layer. A p-channel MOS field effect transistor and an n-p-n bipolar transistor are formed in the n-type epitaxial layer. A p+-type buried layer is also formed over the p-type semiconductor substrate. A p-type region is formed over the p+-type buried layer. An n-channel MOS field effect transistor and a p-n-p bipolar transistor are formed in the p-type region. The MOS transistors and the bipolar transistors are formed in the n-type epitaxial layer and the p-type region. In each of the n-type epitaxial layer and the p-type region, the MOS field effect transistor and the bipolar transistor commonly use the drain region and the base region so as to increase the density of the integration of the Bi-CMOS semiconductor device.
The above circuit structure can be applicable only to the invertor circuit, but it is difficult to apply the above circuit structure to the circuits wherein the CMOS device and the bipolar transistors receive different power voltages.
In the Japanese patent publication No. 7-44231, it is disclosed that the Bi-CMOS semiconductor device has an island structure of the CMOS device region in order to prevent noises generated from the CMOS device from providing influences to the bipolar transistors.
A p-well is provided between the CMOS device region and the bipolar transistor region wherein the p-well extends downwardly to reach a p-type semiconductor substrate so that the p-well electrically isolates the CMOS device region from the bipolar transistor region.
Since, however, the provision of the n-well region and the p-well region for isolation between the CMOS device region from the bipolar transistor region makes it difficult to increase the density of the integration.
In the above circumstances, it had been required to develop a novel Bi-CMOS semiconductor device free from the above problems.